VLSI Design - oalib

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VLSI Design

ISSN Print: 1065-514X

ISSN Online:

主页: http://www.hindawi.com/journals/vlsi/

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Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications

Yeong-Kang Lai,Yeong-Lin Lai,Thomas Schumann

New Algorithmic Techniques for Complex EDA Problems

Shantanu Dutt,Dinesh Mehta,Gi-Joon Nam

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Syed Asad Alam,Oscar Gustafsson

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

S. Syed Ameer Abbas,S. J. Thiruvengadam,S. Susithra

VLSI Architectures for Image Interpolation: A Survey

C. John Moses,D. Selvathi,V. M. Anne Sophia

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic

Wafi Danesh,Jaya Dofe,Qiaoyan Yu

Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Marwan A. Jaber,Daniel Massicotte

Low-Area Wallace Multiplier

Shahzad Asif,Yinan Kong

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

Khader Mohammad,Ahsan Kabeer,Tarek Taha

Gate-Level Circuit Reliability Analysis: A Survey

Ran Xiao,Chunhong Chen

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

Daniel Llamocca,Marios Pattichis

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Shikha Panwar,Mayuresh Piske,Aatreya Vivek Madgula

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Kaiyu Wang,Qingxin Yan,Shihua Yu,Xianwei Qi,Yudi Zhou,Zhenan Tang

Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

Sahar Arshad,Muhammad Ismail,Usman Ahmad,Anees ul Husnain,Qaiser Ijaz

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Deepa Yagain,A. Vijaya Krishna

Parallel Jacobi EVD Methods on Integrated Circuits

Chi-Chia Sun,Jürgen G？tze,Gene Eu Jan

Design of Smart Power-Saving Architecture for Network on Chip

Trong-Yen Lee,Chi-Han Huang

Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design

Yu-Cheng Fan,Chih-Kang Lin,Shih-Ying Chou,Chun-Hung Wang,Shu-Hsien Wu,Hung-Kuan Liu

High-Efficient Circuits for Ternary Addition

Reza Faghih Mirzaee,Keivan Navi,Nader Bagherzadeh

On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

Vadim Geurkov,Lev Kirischian

Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

Christopher Bailey,Brendan Mullane

Advanced VLSI Architecture Design for Emerging Digital Systems

Yu-Cheng Fan,Qiaoyan Yu,Thomas Schumann,Ying-Ren Chien,Chih-Cheng Lu

Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera

Yu-Cheng Fan,Yi-Feng Chiang

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

Shadi Traboulsi,Valerio Frascolla,Nils Pohl,Josef Hausner

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Mauro Olivieri,Antonio Mastrandrea

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

A. Kishore Kumar,D. Somasundareswari,V. Duraisamy,T. Shunbaga Pradeepa

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Hiroki Iwaizumi,Shingo Yoshizawa,Yoshikazu Miyanaga

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

Ching-Lung Su,Tse-Min Chen,Kuo-Hsuan Wu

LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization

Tinoosh Mohsenin,Houshmand Shirani-mehr,Bevan M. Baas

High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

Ting-Li Chu,Sin-Hong Yu,Chorng-Sii Hwang

A 0.6-V to 1-V Audio Modulator in 65？nm CMOS with 90.2？dB SNDR at 0.6-V

Liyuan Liu,Dongmei Li,Zhihua Wang

Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection

Francesco Colonna,Mariagrazia Graziano,Mario R. Casu,Xiaolu Guo,Maurizio Zamboni

Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems

Masahide Hatanaka,Toru Homemoto,Takao Onoye

Faster and Energy-Efficient Signed Multipliers

B. Ramkumar,Harish M. Kittur

Design a Bioamplifier with High CMRR

Yu-Ming Hsiao,Miin-Shyue Shiau,Kuen-Han Li,Jing-Jhong Hou,Heng-Shou Hsu,Hong-Chong Wu,Don-Gey Liu

Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

Bisrat Tafesse,Venkatesan Muthukumar

Ingredients of Adaptability: A Survey of Reconfigurable Processors

Anupam Chattopadhyay

Power-Driven Global Routing for Multisupply Voltage Domains

Tai-Hsuan Wu,Azadeh Davoodi,Jeffrey T. Linderoth

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

Shadi Traboulsi,Valerio Frascolla,Nils Pohl,Josef Hausner,Attila Bilgic

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Mauro Olivieri,Antonio Mastrandrea

Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera

Yu-Cheng Fan,Yi-Feng Chiang

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Hiroki Iwaizumi,Shingo Yoshizawa,Yoshikazu Miyanaga

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

A. Kishore Kumar,D. Somasundareswari,V. Duraisamy,T. Shunbaga Pradeepa

Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

Huan Ren,Shantanu Dutt

A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

Hou-Ming Chen,Robert C. Chang,Kuang-Hao Lin

Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver

Diego Javier Reinoso Chisaguano,Minoru Okada

Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Carna Radojicic,Christoph Grimm,Florian Schupfer,Michael Rathmair

Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

Ching-Hwa Cheng

FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders

David H. K. Hoe,L. P. Deepthi Bollepalli,Chris D. Martinez

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Shipra Upadhyay,R. K. Nagaria,R. A. Mishra

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