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OALib Journal期刊
ISSN: 2333-9721
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ISSN Print: 1687-7195

ISSN Online:

主页: https://www.hindawi.com/journals/ijrc/

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Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

El-Araby, Esam,Mahmud, Naveed

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Fang, Xin,Ioannidis, Stratis,Leeser, Miriam

FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

Das, Nitish,P, Aruna Priya

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Fengler, Wolfgang,Kerling, Philipp,Kirchhoff, Michael,Streitferdt, Detlef

From FPGA to Support Cloud to Cloud of FPGA: State of the Art

Fresse, Virginie,Jamont, Jean Paul,Malek, Jihene,Skhiri, Rym,Suffran, Benoit

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

Nabi, Syed Waqar,Vanderbauwhede, Wim

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Ait El Cadi, Abdessamad,Ali, Karim M. A.,Ben Atitallah, Rabie,Dekeyser, Jean-Luc,Fakhfakh, Nizar

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Giorgi, Roberto,Khalili, Farnam,Procaccini, Marco

An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

Benelli, Gionata,Dinelli, Gianmarco,Fanucci, Luca,Meoni, Gabriele,Rapuano, Emilio

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

Vipin, Kizheppatt

Exposing End-to-End Delay in Software-Defined Networking

Liu, Bin,Zhang, Ting

Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs

Banks, Jasmine E.,Kelson, Neil A.,Macintosh, Hamish J.

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